Advances in very large scale integration (VLSI) fabrication techniques for integrated circuits (IC) are often based on reduced transistor dimensions (e.g., channel length) without a proportional scaling of the reference voltages. The reduction of critical transistor dimensions results in a significant increase of the electrical fields in the transistors. When for example, a N-channel field effect transistor (N-FET) is conductive in the deep saturation region, then its gate oxide can be damaged by high electrical fields. The results are, for example, longer delay times and a lower long-term reliability of the IC. Consequences known in the art under the terms `hot-carrier induced degradation` and `hot electron effects` are described in Leblebici, Y.: "Design Considerations for CMOS Digital Circuits with Improved Hot-Carrier Reliability", IEEE J. of Solid State Circuits, vol. 31, No. 7, p. 1014-1024 (1996) 2!.
FIGS. 1-2 explain details of the problem which is reduced or solved by the present invention. FIG. 1 is a simplified circuit diagram of a prior art electronic system 11 having first circuit 10 and second circuit 20. Electronic system 11 represents an I/O (input/output) connection. Circuits 10 and 20 are coupled by signal line 15 and reference line 19. Signal line 15 is also referred to as "PAD".
Circuit 10 receives a low supply voltage V.sub.CC 1 (e.g., V.sub.CC 1 =3.3 volts) at supply line 91; and circuit 20 receives a higher supply voltage V.sub.CC 2 (e.g., V.sub.CC 2 =5.5 volts) at supply line 92, so that: EQU V.sub.CC 1 &lt;V.sub.CC 2. (1)
V.sub.PAD is the potential between lines 15 and 19 and can be: EQU 0&lt;V.sub.PAD &lt;V.sub.CC 2. (2)
Circuit 10 comprises N-FETs N2 and N1 serially coupled with drain (D) and source (S) electrodes between signal line 15 and reference line 19. A gate (G) of N-FET 1 is coupled to input terminal 90; and a gate (G) of N-FET N2 is coupled to supply line 91 at V.sub.CC 1. Voltages across D and S of N-FET N1 and N-FET N2 are V.sub.DS 1 and V.sub.DS 2, respectively. N-FETs N1 and N2 are voltage sensitive components, whose V.sub.DS 1 and V.sub.DS 2 should not exceed a critical voltage ("break voltage") V.sub.DS MAX : EQU V.sub.DS 1,2 .ltoreq.V.sub.DS MAX ( 3)
when either of N-FETs N1 or N2 is conductive. When N-FETs N1 and N2 are not conductive, then V.sub.DS 1,2 can exceed V.sub.DS MAX. It is inconvenient, when V.sub.DS MAX is lower than V.sub.CC 2 : EQU V.sub.DS MAX &lt;V.sub.CC 2 ( 4)
In circuit 20, switch 25 is coupled between supply line 92 and signal line 15. The operation of switch 25 is not communicated to circuit 10. Circuit 20 can temporarily pull V.sub.PAD (signal line 15) to the higher supply voltage V.sub.CC 2 so that N-FETs N1 and N2 could be damaged.
FIG. 2 is a simplified voltage-time diagram illustrating the operation of system 11 of FIG. 1 by way of example. FIG. 2 refers to a pull-down operation when N-FETs N1 and N2 pull line 15 to line 19. A pull-up operation in the opposite direction is not considered. Traces 31-32 for V.sub.PAD and traces 41-43 for V.sub.DS1 are coordinated by a vertical voltage-axis "V" (0 volts to V.sub.CC 2 =5.5 volts) and a horizontal time-axis "t" (in nano seconds ns). Line 51 between traces 31 and 41 and lines 52-53 between traces 32 and 43 show: EQU V.sub.DS 2 =V.sub.PAD -V.sub.DS 1 ( 5)
It is assumed that V.sub.DS MAX is about 3.6 volts. In a time interval between t=0 and t=t.sub.1, (e.g., at t.sub.1 =2 ns), V.sub.PAD is at its maximum value V.sub.CC 2 =5.5 volts (trace 31, equation 2). N-FETs N1 and N2 are not conducting. N-FET N1 adds its V.sub.DS 2 (line 51) to V.sub.DS 1 of N-FET N1 (trace 41), thus fulfilling condition (3).
At time t.sub.1, N-FET N1 is made conductive by, e.g., an input signal at its gate G (input terminal 90), and V.sub.DS 1 goes quickly to substantially zero (at 0.5 volts, trace 42) so that N-FET N1 is not damaged. In the interval after t.sub.1, V.sub.DS 1 stays at zero (trace 43). However, V.sub.PAD decreases slowly (trace 32), so that between t.sub.1 and t.sub.2, V.sub.DS 2 (line 52) exceeds temporarily V.sub.DS MAX. V.sub.DS 2 across N-FET N2 reaches its allowable value V.sub.DS 2 =V.sub.DS MAX only at t.sub.2 (equation 3, line 53).
In FIG. 3 of related application 1!, a control circuit (reference number 20) switches the gate of N-FET N2 (signal G2) alternatively between a voltage VCCL (corresponding to V.sub.CC 1 in FIG. 1) and VCCH (corresponding to V.sub.CC 2). With a temporarily increased conductivity of N-FET N2, voltage V.sub.DS 2 falls faster so that the time interval t.sub.1 and t.sub.2 can be reduced. However, such a solution is not always applicable, because circuit 10 would require two supply voltages (V.sub.CC 1 and V.sub.CC 2). This is especially difficult to implement when circuit 10 and circuit 20 separated by a significant distance.
There is a need to design an I/O connection which mitigates or avoids these and other disadvantages and limitations of the prior art.